1. Field of the Invention
This invention relates to interface circuit design and, more particularly, to an input buffer design including low voltage transistors and a single low voltage power supply.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
A current trend in integrated circuit (IC) design is that internal power supply levels continue to fall, while external power supply levels remain substantially unchanged. For example, extended high speed transistor logic (eHSTL) with voltage swings between about 0.0V and 1.8V is often used for inter-IC signaling, even though the IC's themselves may operate at significantly lower levels (e.g., about 1.2V to about 1.8V). To provide compatibility with higher power supply systems (such as those utilizing eHSTL), an interface circuit may be incorporated within an IC for translating higher voltage signals to lower voltage signals. For example, an interface circuit may include a voltage translator, level shift circuit or level clipping circuit, and may be placed in the signal path preceding an input buffer portion of the interface circuit.
To accommodate lower internal power supply voltages (e.g., about 1.45V and below), the input buffer portion may include a pair of low voltage input transistors, which are coupled together for receiving a relatively low voltage (e.g., about 1.45V) from a low voltage power supply. The pair of input transistors may also receive a high voltage input signal or a pair of high voltage input signals (e.g., 1.8V) from input pins or another integrated circuit. The input signals supplied to the pair of input transistors may be differential or single-ended, depending on design specifications. In some cases, a differential amplifier may be coupled to output nodes of the input transistors for generating an output voltage based on a comparative difference between the input signals supplied to the input transistors.
However, a problem often arises when a high voltage input signal (e.g., above about 1.45 V for CMOS process technologies) is supplied to a low voltage transistor. As used herein, a low voltage transistor may be generally described as having a thinner gate oxide and/or different source/drain doping than a high voltage transistor. In addition, low voltage transistors tend to be smaller than their high voltage counterparts and are typically optimized for operating within a lower voltage range (e.g., about 0.0V to 1.45V for CMOS), depending on the particular process technology used. Unlike high voltage transistors, which are optimized for operating within a higher voltage range (e.g., about 0.0V to about 1.8V for CMOS), low voltage transistors often experience some level of degradation when gate-to-drain (or gate-to-source) voltages exceed the upper threshold of the operating range (e.g., about 1.45V). In other words, gate voltages in excess of about 1.45V tend to overstress the thinner gate oxides of low voltage CMOS transistors, often resulting in gate oxide degradation or breakdown. Performance issues arise when the gate oxide begins to degrade, with circuit failure occurring when the gate oxide reaches breakdown.
Therefore, a need remains for an improved interface circuit capable of translating a relatively high external voltage into a relatively low internal voltage without experiencing gate oxide degradation or breakdown.